This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. xc2xa7119 from my application SYSTEM AND METHOD FOR CONTROLLING A SYNCHRONOUS DEVICE AND AN ASYNCHRONOUS DEVICE CONNECTED TO AN INTER-INTEGRATED CIRCUIT BUS (I2C BUS) filed with the Korean Industrial Property Office on Jun. 30, 1998 and there duly assigned Serial No. 25470/1998.
1. Field of the Invention
This present invention relates to a technique for controlling synchronous devices and asynchronous devices which are connected to an inter-integrated circuit bus (I2C bus), and more particularly relates to a technique for controlling synchronous slave devices and asynchronous master devices connected to an inter-integrated circuit bus which analyzes requests and responses of the asynchronous master devices and the synchronous slave devices and provides a common interface.
2. Description of the Related Art
In an earlier structure of a system for controlling a slave device, a system connected to an I2C bus comprises an application program block, a microcontroller device driver for driving a microcontroller in accordance with the application program block""s command, a central processing unit (CPU), a system memory connected to the CPU and a system bus, a shared memory, the microcontroller controlling slave devices in accordance with the microcontroller device driver""s request and a plurality of slave devices connected to the I2C bus.
When a request to control devices connected to an I2C bus is made from an application program block, the earlier method for controlling a slave device comprises opening a device as an initialization for accessing the device, device-writing to perform the access and the request for controlling the device, device-reading to access the device and process the reply if there is a reply from the slave device, and device-closing, that is ending the access to the device.
However, such a system for controlling slave devices has a shared memory only including a microcontroller information saving area, a slave device controlling area, a slave device commanding area and a slave device response area, and so the controlling system considers only the slave devices and performs processing on only the slave devices but not on the master devices.
The following patents disclose features in common with the present invention but do not teach or suggest the technique for controlling synchronous devices and asynchronous devices connected to an I2C bus as in the present invention: U.S. Pat. No. 5,199,106 to Bourke et al., entitled INPUT OUTPUT INTERFACE CONTROLLER CONNECTING A SYNCHRONOUS BUS TO AN ASYNCHRONOUS BUS AND METHODS FOR PERFORMING OPERATIONS ON THE BUS, U.S. Pat. No. 5,276,814 to Bourke et al., entitled METHOD FOR TRANSFERRING INFORMATION BETWEEN MAIN STORE AND INPUT OUTPUT BUS UNITS VIA A SEQUENCE OF ASYNCHRONOUS BUS AND TWO SYNCHRONOUS BUSES, U.S. Pat. No. 5,293,603 to MacWilliams et al, entitled CACHE SUBSYSTEM FOR MICROPROCESSOR BASED COMPUTER SYSTEM WITH SYNCHRONOUS AND ASYNCHRONOUS DATA PATH, U.S. Pat. No. 5,793,996 to Childerse et al., entitled BRIDGE FOR INTERCONNECTING A COMPUTER SYSTEM BUS, AN EXPANSION BUS AND A VIDEO FRAME BUFFER, U.S. Pat. No. 5,835,785 to Overtoom et al., entitled MULTIPLEXED THREE LINE SYNCHRONOUS/FULL-DUPLEX ASYNCHRONOUS DATA BUS AND METHOD THEREFOR, U.S. Pat. No. 5,774,680 to Wanner et al., entitled INTERFACING DIRECT MEMORY ACCESS DEVICES TO A NON-ISA BUS, U.S. Pat. No. 5,615,404 to Knoll et al., entitled SYSTEM HAVING INDEPENDENTLY ADDRESSABLE BUS INTERFACES COUPLED TO SERIALLY CONNECTED MULTI-PORTED SIGNAL DISTRIBUTORS GENERATING AND MAINTAINING FRAME BASED POLLING SCHEDULE FAVORING ISOCHRONOUS PERIPHERALS, U.S. Pat. No. 5,564,025 to De Freese et al., entitled APPARATUS FOR ARBITRATING REQUESTS FOR ACCESS FROM SLAVE UNITS BY ASSOCIATING THE REQUESTS WITH MASTER UNITS AND DETERMINING THE RELATIVE PENDENCY THEREOF IN A RADIO BASE STATION TRANSCEIVER, U.S. Pat. No. 5,590,369 to Burgess et al., entitled BUS SUPPORTING A PLURALITY OF DATA TRANSFER SIZES AND PROTOCOLS, U.S. Pat. No. 5,309,567 to Mizukami, entitled STRUCTURE AND METHOD FOR AN ASYNCHRONOUS COMMUNICATION PROTOCOL BETWEEN MASTER AND SLAVE PROCESSORS, U.S. Pat. No. 5,434,983 to Yaso et al., entitled DATA PROCESSING APPARATUS HAVING FIRST BUS WITH BUS ARBITRATION INDEPENDENT OF CPU, SECOND BUS FOR CPU, AND GATE BETWEEN FIRST AND SECOND BUSES, U.S. Pat. No. 5,892,931 to Cohen et al., entitled METHOD AND APPARATUS FOR SPLITTING A BUS TARGET RESPONSE BETWEEN TWO DEVICES IN A COMPUTER SYSTEM, U.S. Pat. No. 5,857,083 to Venkat, entitled BUS INTERFACING DEVICE FOR INTERFACING A SECONDARY PERIPHERAL BUS WITH A SYSTEM HAVING A HOST CPU AND A PRIMARY PERIPHERAL BUS, U.S. Pat. No. 5,878,237 to Olarig, entitled APPARATUS, METHOD AND SYSTEM FOR A COMPUTER CPU AND MEMORY TO PCI BRIDGE HAVING A PLURALITY OF PHYSICAL PCI BUSES, U.S. Pat. No. 5,881,255 to Kondo et al., entitled BUS CONTROL SYSTEM INCORPORATING THE COUPLING OF TWO SPLIT-TRANSACTION BUSSES OF DIFFERENT HIERARCHY, and U.S. Pat. No. 5,809,261 to Lambrecht, entitled SYSTEM AND METHOD FOR TRANSFERRING DATA STREAMS SIMULTANEOUSLY ON MULTIPLE BUSES IN A COMPUTER SYSTEM.
The present invention is designed to solve the above problems. It is an object of the present invention to provide a technique for controlling synchronous devices and non-synchronous devices connected to an inter-integrated circuit bus, which technique analyzes requests and responses of non-synchronous master devices and synchronous slave devices and provides a common interface.
Other objects and advantages of the present invention will become apparent with reference to the following detailed description and the attached drawings.
In a system including a central processing unit (CPU) connected to a system bus, a system memory connected to the system bus, a shared memory connected to the system bus for storing information about a variety of devices which are connected to the I2C bus, a microcontroller connected to the I2C bus for communicating with the shared memory and for controlling the devices which are connected to the I2C bus, and a plurality of synchronous slave devices which are controlled by the microcontroller and are each connected to a first I2C bus, a system for controlling synchronous and non-synchronous devices connected to an inter-integrated circuit bus (I2C bus) comprises a plurality of non-synchronous master devices which are controlled by the microcontroller and are connected to a second I2C bus, and a third I2C bus for connecting the first I2C bus to the second I2C bus.
In a system connected to an inter-integrated circuit bus (I2C bus), which includes non-synchronous master devices, synchronous slave devices, a shared memory for saving information about the devices, an application program for controlling the devices through the shared memory, and a microcontroller device driver, a method of controlling synchronous and non-synchronous devices comprises the steps of accessing the devices through the shared memory for saving information about the non-synchronous master devices and synchronous slave devices in the same manner, regardless of the type of device, when there is a request for controlling the devices, performing the controlling request according to each device through the shared memory by the application program, and processing responses from the devices by the shared memory and the microcontroller device driver.